==== The E.V.I.L. Microarchitecture ====
~~hero-subtitle An Embedded, Variable Instruction Length bit-serial CPU architecture.~~

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| This page is written in a //stream of consciousness// style, as gathered notes from various sources and past discussions.  |
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| Formatting and proper layout are not final, or even specified in a way that matters.  |
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| Revisions to make this page more approachable and fitting of the representative quality of //significant bit// pages or postings, are planned for the future.  |

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    * The instruction encoding is very simple - in fact, it is the simplest that instruction encoding can possibly be.
      * 0 is NOP; 1 is OP.
        * If you hit NOP, go to next bit and continue.
        * If you hit OP, then go to next bit, and see what operation it is.
        * After OP you then have eight classes of instruction, given by three binary decisions: memory/register; ALU/copy; I/O ports/bus memory.
    * In effect, it is a 1-bit CPU architecture that does nothing, if all you feed it is zero bits.
    * It can be self-clocking, as the instruction encoding is meant to not enable long run-lengths of the same bit.
      * Except 0, which is not only NOP, but also static, default, halt.
      * A 1 following the NOP acts as both the clock and interrupt pulse.
    * The goal here isn't to run fast, or even run well.
      * it is minimal computing hardware without going to absolute turing tarpit status.
    * Bit-serial CPUs have a handful of advantages:
      * Bit-serial CPUs are minimal in terms of cost and requirements.
        * Sometimes they don't even need a +Vcc; they'll work on quiescent current and operate with bus voltage.
          * Obvious power-saving benefit there, too.
      * A bit-serial CPU embeds well for minimal state control and programmable logic in places you wouldn't expect.
        * Places like an addressible, color LED cell, similar to the WS2812 and similar series.
      * If you need complex, programmable machinery, with memory, in an extremely limited die space, a bit-serial architecture can make it work.
        * I'm thinking something along the terms of targeted drug delivery. You have a tiny, biocompatible and inert chip with minimal, energy harvesting running current, a few hundred bytes of ROM and RAM, an electrochemical enzyme sensor on a digital port, and another protein structure that unfolds when an electric charge is applied, releasing a molecule of targeted therapy into the surrounding tissue.
          * You wouldn't be able to embed much more than a bit-serial ISA in there, but you need a programmable computer to determine what the hysteresis and trigger values are for the input sensor molecule.
          * So, if you're planting several hundreds of this chip onto dose-regulated particles, it can sense when it needs to release the drug more efficiently than state machinery or a logic circuit.
        * The complexity space for a bit-serial micro falls squarely where silicon real estate is at a premium, and where a logic circuit would take significantly more space to implement than a programmed memory cell.
        * A bit-serial computer uses less space and energy to progress through complex processing with memory, like the case mentioned above.